The Observation of Width Quantization Impact on Device Performance and Reliability for High-k/Metal Tri-Gate FinFET

Abstract

In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrier conduction in the trapezoidal shape Si-fin body of FinFETs is different for devices with different Fin bottom widths (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fin_bottom</sub> ), which will impact the device performance and reliability. For n-type FinFETs, the experimental results show that the thinner W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fin_bottom</sub> device performs better reliability under HCI stress due to higher inversion carrier density at the center of Si-fin channel. For p-type FinFETs under negative bias stressing, the thinner W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fin_bottom</sub> device shows more serious degradation on drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) and subthreshold swing (SS) with the increasing of stressing voltage due to larger electric field within the Si-fin and higher energy of inversion holes, while the thicker W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fin_bottom</sub> device shows almost insensitively degradation with the variation of stressing voltage.