Advances in the Super-Lattice Castellated Field Effect Transistor (SLCFET) for wideband low loss RF switching applications

Abstract

The Super-Lattice Castellated Field Effect Transistor (SLCFET) uses a super-lattice in the channel region to form multiple parallel current paths in conjunction with castellations etched into that super-lattice to provide a sidewall gate structure. The sidewall gate permits the gate applied electric field to penetrate between the parallel 2DEG layers, allowing the carriers to be depleted out prior to avalanche breakdown within the material, as would occur with a conventional gate structure. Using an AlGaN/GaN super-lattice, we report on this method as a way to scale RF switch performance, decreasing ON resistance without significantly increasing OFF capacitance, with a median measured ON resistance of 0.38 Ω-mm and a median measured OFF capacitance of 0.21 pF/mm, leading to an RF switch figure of merit, F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CO</sub> =2.0 THz. 90/10 and 10/90 fall and rise times for the SLCFET have been measured to be faster than 100 nsec, while the RF power handling for a series SLCFET has been measured at 10 GHz to be greater than 10 W without loss compression. Wideband SPDT RF switch performance over a 0.5-20 GHz bandwidth with <;|-0.3| dB of insertion loss and >|-30| dB of isolation has been achieved.