A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector

Abstract

A 400 Mb/s ~2.5 Gb/s referenceless clock and data recovery (CDR) IC is presented. This paper shows that the half-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability in itself. By using this intrinsic frequency detection capability of the half-rate linear PD, a CDR can be implemented in the single loop architecture without both an external reference clock and a separate frequency detector. For verification, a prototype CDR IC was fabricated in a 0.13 μm CMOS process. With 2.5 Gb/s, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 pseudorandom binary sequence (PRBS), the measurement results show that the frequency acquisition time is 17 μs, the bit error rate (BER) is better than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> , the jitter of the recovered clock is 8.6 psrms and the out-of-band jitter tolerance is 0.32 UI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> .