A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization

Abstract

Single-mode wavelength-division multiplexing (WDM) optical links are an attractive technology to meet the growing interconnect bandwidth demand in data center applications. This paper presents a multi-channel hybrid-integrated photonic receiver based on microring drop filters and waveguide photodetectors implemented in a 130 nm SOI process and high-speed optical front-ends designed in 65 nm CMOS. The source-synchronous receiver utilizes an LC injection-locked oscillator (ILO) in the clock path for improved jitter filtering, while maintaining correlated jitter tracking with the data channels. Receiver sensitivity is improved with a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE). In order to stabilize the microring drop filter resonance wavelength, a peak-detector-based thermal tuning loop is implemented with a 0.7 nm range at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$43~\mu \text {W}$ </tex-math></inline-formula> /GHz efficiency. When tested with a waveguide photodetector with 0.45 A/W responsivity, the receiver achieves -8.0 dBm OMA sensitivity at a BER <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$= 10^{\mathrm {-12}}$ </tex-math></inline-formula> with a jitter tolerance corner frequency near 20 MHz and a per-channel power consumption of 17 mW including amortized clocking power.