A novel approach for incorporating silica filler into no-flow underfill

Abstract

No-flow underfill technology has been proven to have potential advantages over the conventional underfill technology. However, due to the filler entrapment between solder bump and contact pad on board, no-flow underfills are mostly unfilled or filled with very low filler loading. The high coefficient of thermal expansion (CTE) of the polymer material has significantly lowered the reliability of flip chip assembly using no-flow underfill, and has limited its application to large chip assemblies. This paper presents a novel approach to incorporate silica filler into no-flow underfill. Two layers of underfills are applied on to the substrate before chip placement. The bottom underfill layer facing the substrate is fluxed and unfilled; the upper layer facing the chip is filled with 65 wt% silica fillers. The total filler loading of the mixture is estimated to be around 55 wt% using Thermo-Gravimetric Analyzer (TGA). The material properties of each layer of underfills and the underfill mixtures are characterized using Differential Scanning Calorimeter (DCS), Thermo-Mechanical Analyzer (TMA), Dynamic Mechanical Analyzer (DMA), and stress rheometer. FB250 daisy-chained test chips are assembled on FR-4 boards using the novel approach. A 100% yield of solder interconnect is achieved with filled no-flow underfill for the first time. Wetting of the eutectic SnPb solder to contact pad on the board is confirmed by Scanning Electronic Microscopy (SEM) and optical microscopic observation. An US patent is filed for this invention. The failure in normal no-flow underfill. Assembly with silica filler is investigated. Other variations of this process are discussed.