2016 · 24 citations · 2 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ScalingIntegrated Circuit DesignShort-channel EffectsVoltage ScalingWide Band Gap SemiconductorsBreakdown VoltageIntegrated Passive DevicesLow-voltage Cmos DesignMetallizationPower MosfetsUltra-low-power Cmos
In this paper, we present the integration of RESURF high-voltage lateral Power MOSFETs which achieve highly competitive figures of merit (such as Rsp, defined as Rdson*Area) in a Trench-Isolated 0.18 micron 100V-rated BCD technology. The new high-voltage LDMOS are rated for operation up to 45V, 60V, 80V and 100V and achieve BVdss & Rsp of 55V/32 mOhm*mm2, 75V/57 mOhm*mm2, 100V/91 mOhm*mm2 and 128V/206 mOhm*mm2 respectively. The HV devices are integrated with high-performance and fully isolated 8V to 30V LDMOS with low Rsp, 1.8V and 5V CMOS, as well as bipolar devices, diodes and other passive devices. The devices are isolated laterally using 20 micron deep trenches with air-gap, for low stress and minimized capacitance. Large 1mm2 Power MOSFETs were fabricated and characterized in order to determine the “effective Rsp“ including metallization, using a three metal back-end with 4um thick top aluminum metallization.
2
BCD (Bipolar-CMOS-DMOS) technology trends for power management IC
Il-Yong Park, Yong-Keon Choi, Kwang-Young Ko et al. · 2011 · 27 citations
Engineering, Computer Engineering, Electrical Engineering +17
Scaling issues in lateral power MOSFETs
Mohammad Darwish, J. Huang, Meilin Liu et al. · 2002 · 25 citations