An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS

Abstract

This paper demonstrates an asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture with an embedded passive gain technique for lowpower and high-speed operation. The proposed passive gain technique relaxes the noise requirement of the comparator and reuses the existing capacitor DAC in SAR for minimal overhead. An additional time-out scheme is adopted to advance the SAR conversion whenever the comparator takes longer time to resolve, which improves the overall conversion rate. To prove the concept, an 11-bit ADC prototype was fabricated in 65 nm CMOS technology. The prototype measured a peak effective number of bits (ENOB) of 10.2 and a spurious-free dynamic range (SFDR) of 75.2 dB at a 95-MS/s sampling rate with 1.36-mW power consumption from a 1.1 V supply. The measured static differential nonlinearity (DNL) and integral nonlinearity (INL) were less than ± 0.84 LSB with a differential input swing of 1.6 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> .