Jae-Won Nam - Concepedia

Author

Jae-Won Nam

University of Southern California ORCID

Also Known As

J.-J. Nam, Jae-Won Nam, Nam, Jae-Won

Publications

333

Citations

H-Index

Concepts

All Affiliations

University of Southern California Electronics and Telecommunications Research Institute Seoul National University of Science and Technology

About

Jae-Won Nam is an author at University of Southern California specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	8	8	217
2	Engineering	4	4	158
3	Computer Architecture	2	2	34
4	Electrical Engineering	1	1	21
5	Analog System Engineering	1	1	52

Jae-Won Nam

Publications

246

Citations

H-Index

Page 1

	Year	Citations
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, IEEE Journal of Solid-State Circuits RadarAdc Prototype12-Bit 1.6EngineeringSynthetic Aperture Radar	2018	72
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique Young‐Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, IEEE Transactions on Circuits & Systems II Express Briefs EngineeringAnalog System EngineeringData ConverterMixed-signal Integrated CircuitAnalog Design	2010	52
Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique Jae-Won Nam, Ju-Hyeok Ahn, Jong-Phil Hong IEEE Access Low-power ElectronicsHardware SecurityElectrical EngineeringEngineeringVlsi Design	2022	21
Quantification of endogenous gibberellins in leaves and tubers of Chinese yam, Dioscorea opposita Thunb. cv. Tsukune during tuber enlargement Sang-Kuk Kim, Sang‐Chul Lee, Dong‐Hyun Shin, Plant Growth Regulation	2003	19
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture Young-Deuk Jeon, Jae-Won Nam, Kwi-Dong Kim, IEEE Transactions on Circuits & Systems II Express Briefs Data ConverterMixed-signal Integrated CircuitAnalog DesignDual-channel Pipelined AdcComputer Engineering	2012	17
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS Jae-Won Nam, Mike Shuo‐Wei Chen IEEE Transactions on Circuits and Systems I Regular Papers Passive Gain TechniqueData ConverterMixed-signal Integrated CircuitNm CmosAnalog Design	2016	16
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Sar Adc12-Bit 1.6Data ConverterMixed-signal Integrated CircuitInterpolation Technique	2016	16
A 9.15mW 0.22mm<sup>2</sup> 10b 204MS/s pipelined SAR ADC in 65nm CMOS Young-Deuk Jeon, Young‐Kyun Cho, Jae-Won Nam, Sar AdcEngineeringData ConverterMixed-signal Integrated CircuitAnalog Design	2010	13
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS Jae-Won Nam, David Chiong, Mike Shuo‐Wei Chen Passive Gain TechniqueAnalog-to-digital ConverterData ConverterMixed-signal Integrated CircuitAnalog Design	2013	10
A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array Young‐Kyun Cho, Jae-Won Nam, Sangwon Lee IEEE Transactions on Circuits & Systems II Express Briefs	2021	10

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