A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method

Abstract

This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.