EngineeringComputer EngineeringComputer ScienceComputer ArchitectureParallel ComputingSystem-on-chip DesignInstruction Set ArchitectureMemory Hierarchy DesignMemory Hierarchy OptimizationMemory Subsystem DesignMicroarchitecture DesignPhysical DesignCrossbar Switch DesignCrossbar SwitchesCrossbar SwitchingMemory Interface ArchitectureMemory Interface DesignMemory Management InterfaceSupercomputer ArchitectureSystem-on-chip Hierarchy
This article consists of a collection of slides from the author's conference presentation covering the following topics: IBM Blue Gene/Q development; massively parallel supercomputing systems; BlueGene/Q compute chip; system-on-a-chip design; BG/Q processor unit; crossbar switch; L2 cache; DDR3 memory interface; networking logic; physical-to-logical PUnit mapping; and Blue Gene/Q packaging hierarchy.