2016 · 27 citations · 7 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureFault-tolerant ComputingStorage SystemsErasure CodingFault-tolerant Storage SystemsMemory DevicesMemory HierarchyMemory Hierarchy OptimizationStorage Fault ToleranceBandwidthEndurance OptimizationParity-based StorageSystem-level ModelingSystem-level OptimizationWrite LatencyWrite Latency Optimization
We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new program sequence, called relaxed program sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.
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A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology
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Engineering, Computer Engineering, Electrical Engineering +15