On-Board Silicon Photonics-Based Transceivers With 1-Tb/s Capacity

Abstract

Providing host Application-specific integrated circuit (ASIC) (e.g., microprocessors, switches, or field-programmable gate array (FPGAs)) with terabit per second optical transmission capabilities has emerged as a new requirement in exascale cloud data centers and high-performance computing. The combination of silicon photonics (Si-Phot) and 3-D interconnecting technologies stands as a unique solution for fulfilling this need while addressing the key factors of success that are more Gb/s/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , less pJ/bit, and less $/Gb/s. This paper is intended to present and evaluate several Si-Phot-based solutions for providing the host ASIC with 1-Tb/s optical transceivers. Two packaging architectures are proposed, making use of 3-D interconnecting building blocks, and motivated by the need for implementing a few hundreds of high-speed electrical interconnections. Models are given for each of the 3-D building blocks, and simulation of the overall electrical signal integrity is made for the two proposed transceiver architectures. In addition, using the capability of CMOS fabrication lines for producing low-cost transceiver chips (Si-Phot integrated circuits with their electronic ICs) and 3-D chip assemblies, it is also necessary to develop high-throughput/low-cost techniques for coupling the light from the chip to the fiber. One such technique will be presented.