A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

TLDR

Continuous transistor scaling and low‑voltage demands make VLSI circuits, especially large memory arrays, increasingly vulnerable to soft‑errors in space, and conventional radiation hardening via large or redundant bitcells raises area and limits minimum operating voltage, increasing power consumption. The authors propose the first low‑voltage, radiation‑hardened SRAM bitcell that preserves high soft‑error robustness. The 13T design employs a dual‑driven separated‑feedback mechanism that tolerates charge deposits up to 500 fC at a 500‑mV supply, and a 32×32 macro fabricated in 0.18‑µm CMOS operates correctly down to 300 mV. The fabricated macro occupies only twice the area of a standard 6T SRAM cell while maintaining full read/write functionality down to 300 mV.

Abstract

Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Radiation hardening of embedded memory blocks is commonly achieved by implementing extremely large bitcells or redundant arrays and maintaining a relatively high operating voltage; however, in addition to the resulting area overhead, this often limits the minimum operating voltage of the entire system leading to significant power consumption. In this paper, we propose the first radiation-hardened static random access memory (SRAM) bitcell targeted at low-voltage functionality, while maintaining high soft-error robustness. The proposed 13T employs a novel dual-driven separated-feedback mechanism to tolerate upsets with charge deposits as high as 500 fC at a scaled 500-mV supply voltage. A 32×32 bit memory macro was designed and fabricated in a standard 0.18-μm CMOS process, showing full read and write functionality down to the subthreshold voltage of 300 mV. This is achieved with a cell layout that is only 2× larger than a reference 6T SRAM cell drawn with standard design rules.