Material and device engineering in fully depleted silicon-on-insulator transistors to realize a steep subthreshold swing using negative capacitance

Abstract

Abstract This paper discusses material and device engineering in field-effect transistors (FETs) with HfO 2 -based ferroelectric gate insulators to attain a precipitous subthreshold swing (SS) by exploiting negative capacitance. Our physical analysis based on a new concept of a negative dielectric constant reveals that fully depleted silicon-on-insulator (FD-SOI) channels with a modest remnant polarization P r (3 µC/cm 2 at most) are more suitable for realizing SS < 60 mV/decade than a higher P r of 10 µC/cm 2 , which is commonly reported for HfO 2 -based ferroelectric materials. We also confirm SS < 60 mV/decade in more than 5 orders of the subthreshold current in FD-SOI FETs with ferroelectric HfO 2 gate insulators by device simulation.