Design of power optimal, low phase noise three stage Current Starved VCO

Abstract

This paper presents a method for designing of low power dissipation, low phase noise and high oscillation frequency based three stage Current Starved VCO (CS-VCO). In this design approach, 3-inverter stages are cascaded to achieve an optimal power dissipation of (7.48508 mW) for fundamental frequency of (3.9955 GHz). The simulation results depict that such VCO has linear voltage-frequency characteristics over a wide tuning range. The circuit performance is validated using 0.18µm CMOS technology. The analysis also shows that for 3-stage CS-VCO, the phase noise is −80.17dbc/Hz @1MHz offset frequency and −105.31dbc/Hz @10MHz offset frequency.