Graphene Based On-Chip Interconnects and TSVs : Prospects and Challenges

Abstract

In the first four decades of the semiconductor industry, the system performance was entirely dependent on transistor delay and power dissipation. With technology scaling, the transistor delay and power dissipation significantly reduced; however, a negative impact on the interconnect performance was realized. The reduction in the cross-sectional area of copper (Cu) interconnects resulted in higher resistivity under the effects of enhanced grain and surface scattering. Moreover, with smaller interconnect dimensions and higher operating frequency, the performance of Cu interconnects is gradually being limited by the electromigration effect, stability, operational bandwidth, and crosstalk. This trend is forcing researchers to find an alternative solution for high-speed very-large-scale integration (VLSI) interconnects.