IEEE Transactions on Computers · 2016 · 20 citations · 33 references
EngineeringMulti-core SystemsEdge ComputingHigh-performance ArchitectureMany-core ArchitectureComputer EngineeringComputer ArchitectureSystems EngineeringPerformance TuningPrefetcher Aggressiveness ControllersBuffer ManagementComputer SciencePerformance IssueParallel ComputingManycore ProcessorPrefetch Metrics
In multi-core systems, prefetch requests of one core interfere with the demand and prefetch requests of other cores at the shared resources, which causes prefetcher-caused interference. Prefetcher aggressiveness controllers play an important role in minimizing the prefetcher-caused interference. State-of-the-art controllers such as hierarchical prefetcher aggressiveness control (HPAC) select appropriate throttling levels that can lead to improvement in system performance. However, HPAC does not consider the interactions between the throttling decisions of multiple prefetchers, and loses opportunity to improve system performance further. For multi-core systems, state-of-the-art prefetcher aggressiveness controllers controls the aggressiveness based on prefetch metrics such as accuracy, bandwidth consumption and cache pollution. We propose a synergistic prefetcher aggressiveness controller (SPAC), which explores the interactions between the throttling decisions of prefetchers, and throttles the prefetchers based on the improvement in fair-speedup of multi-core systems.
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Nathan Binkert, Bradford M. Beckmann, Gabriel Black et al. · ACM SIGARCH Computer Architecture News · 2011 · 4.8K citations
Engineering, Computer Architecture, Software Engineering +21
Process Variation Tolerant 3T1D-Based Cache Architectures
Xiaoyao Liang, R. Canal, Gu-Yeon Wei et al. · 2007 · 518 citations
Non-volatile Memory, Electrical Engineering, Engineering +12