Complementary Spintronic Logic With Spin Hall Effect-Driven Magnetic Tunnel Junction

Abstract

The conventional CMOS transistors reach its power wall due to the increasing leakage current as technology scales down. The spintronic devices show a great promise as one of the alternatives to replace CMOS technology for the next-generation low-power integrated circuits. Recently, the spintronic memory, e.g., spin-transfer torque magnetic random-access memory, has been successfully commercialized. However, the spintronic logic circuits face critical problems and challenges, such as poor direct cascading ability and small operation gain, before practical applications. In this paper, we propose a complementary spintronic logic (CSL) family based on a novel four-terminal spin Hall effect-driven magnetic tunnel junction (FT-SHE-MTJ). Fully electrically separated write/read paths of the proposed FT-SHE-MTJ device can overcome the challenges of direct cascading and operation gain in current spintronic logic circuits. With the aid of a compact model, the functionality and the performance of the proposed CSL circuits are evaluated. Simulation results show that the correct logic fan-out operation can be achieved with a voltage below 150 mV, which is promising for low-power computing.