Low-Power a-Si:H Gate Driver Circuit With Threshold-Voltage-Shift Recovery and Synchronously Controlled Pull-Down Scheme

Abstract

This paper presents a new low-power gate driver circuit designed by hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). An attempt is also made to reduce the power consumption resulting from the high-frequency pulldown structure, in which a pair of 0.25-Hz clock signals is used to implement a low-frequency and synchronously controlled pull-down scheme for recovering the threshold voltage shifts of a-Si:H TFTs under the negative gate-to-source voltage and decreasing the used TFTs. Measurement results indicate that the proposed gate driver circuit consumes 98.7 μW/stage, and the output waveforms are very stable without distortion when the proposed circuit is operated at 100 °C for 840 h. Furthermore, the feasibility of the proposed gate driver circuit is demonstrated for the quad-extended-video-graphics-array resolution.