Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 0.6–4.2 GHz Current-Reuse CMOS LNA

Abstract

This work examines the use of a forward body biasing (FBB) scheme to mitigate output conductance degradation due to short channel effects in ultra-low voltage (ULV) circuits with no additional power consumption. It is shown that FBB boosts the output resistance of a transistor such that the intrinsic gain reduction due to low-supply voltages can be compensated. This technique is then used to implement a low-noise amplifier (LNA) tailored for ultra-low power (ULP) and ULV applications. The proposed LNA uses common-gate (CG) NMOS transistors as input devices in a complementary current-reuse structure. Low-power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor. Moreover, a separate FBB scheme is exploited to tune the feedback coefficient. An inductive gm-boosting technique is used to increase the bandwidth of the LNA without additional power consumption. The proposed LNA is implemented in an IBM 0.13 μm 1P8M CMOS technology and occupies 0.39 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured LNA has a 14 dB gain, 4 dB minimum noise figure, IIP3 of -10 dBm, and 0.6-4.2 GHz bandwidth, while consuming only 500 μA from a 0.5 V supply. The LNA operates with supplies as low as 0.4 V while maintaining good performance.