Prospects for ferroelectric HfZrOx FETs with experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, switch-off 0.2V, and hysteresis-free strategies

Abstract

Ferroelectric HfZrOx (FE-HZO) FETs is experimentally demonstrated with 0.98nm CET (capacitance equivalent thickness), small hysteresis window VT (threshold voltage) shift <; 0.1V, SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">for</sub> = 42mV/dec, SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rev</sub> = 28mV/dec, and switch-off <; 0.2V. The optimum ALD process leads single monolayer SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> for IL (interfacial layer) and low gate leakage current. The FE-HZO FETs is operated at room temperature and 150K to obtain beyond the physical limitation of Boltzmann tyranny, and the extracted body factors are m = 0.67 and m = 0.89 for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.1 and 0.5 V, respectively, to confirm the negative capacitance (NC) effect. There are two proposed strategies to reach hysteresis-free, including FE-HZO/epi-Ge/Si FETs with experimentally VT shift 3mV in hysteresis window, and 3nm-thick FE-HZO resulting hysteresis-free and sub-0.2V switching by numerical simulation.