10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface

Abstract

The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cutting-edge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]-[5]. With spectrally divided signaling, the multi-band transceiver can be designed to avoid spectral notches with extended communication bandwidth of multi-drop buses [4]. Also, its unique self-equalized double-sideband signaling renders the multi-band transceiver immune to inter-symbol interference caused by channel attenuation without additional equalization circuitry [5]. To further improve the capability and validate the scalability of multi-band signaling, we have realized a tri-band transceiver with four parallel lanes and achieved a total data rate of 40Gb/s, with total power consumption of 38mW in 28nm CMOS technology.