18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface

TLDR

The growing HPC and server markets are driving increased demand for HBM DRAM, prompting customers to seek diverse product families, including high‑bandwidth, low‑density options, and architectures that mitigate process variation in TSV‑based stacked dies. This work introduces an HBM DRAM that supports 4‑, 8‑, and 2‑hi stack configurations while delivering full‑bandwidth performance. The design uses a peripheral base die architecture with address/command decoders, a core pipe‑out generator, and internal power, reference, and bias generators; layout alignment between PHY and TSVs reduces data skew, while a small‑swing technique on the heavy‑load interface cuts dynamic power and improves tolerance to process variations.

Abstract

Because of the expansion of high performance computing (HPC) and server market, demand for HBM DRAM is increasing. With this market flow, diverse customers require various HBM product families. One customer requirement is full bandwidth with less density. Therefore, this work presents a HBM DRAM, which supports 4, 8, and even 2-hi stacks with full-bandwidth performance. The HBM DRAM adopts a peripheral base die architecture, which has smaller chip size and good testability resulting in more manufacturability. This architecture can compensate for process variation, since this problem among core dies within the same known good stacked die (KGSD) is the key issue of TSV-based stacked DRAM [1]. Layout aligning between PHY and TSVs improves the speed performance of the whole system due to reduced data skew. The peripheral base die contains address/command decoders (COMDEC), a core pipe-out (POUT) signal generator, and internal power, references and bias generators. A small-swing technique on a heavy load interface can reduce dynamic power and also has tolerance to process variations.