Manufacturing pathway and experimental demonstration for nanoscale fine-grained 3-D integrated circuit fabric

Abstract

At Sub-20nm technologies CMOS scaling faces severe challenges primarily due to fundamental device scaling limitations, interconnection overhead and complex manufacturing. Migration to 3-D has been long sought as a possible pathway to continue scaling; however, CMOS's intrinsic requirements are not compatible for fine-grained 3-D integration. In [1], we proposed a truly fine-grained 3-D integrated circuit fabric called Skybridge that solves nanoscale challenges and achieves orders of magnitude benefits over CMOS. In Skybridge, device, circuit, connectivity, thermal management and manufacturing issues are addressed in an integrated 3-D compatible manner. At the core of Skybridge's assembly are uniform vertical nanowires, which are functionalized with architected features for fabric integration. All active components are created primarily using sequential material deposition steps on these nanowires. Lithography and doping precision requirements are significantly reduced, and are primarily required in early stages. In this paper, we discuss manufacturing aspects of Skybridge fabric; we introduce Skybridge's manufacturing pathway and show experimental demonstrations of key process steps.