Modulo 2/sup n/ ± adder design using select-prefix blocks

Abstract

We present new design methods for modulo 2/sup n//spl plusmn/1 adders. We use the same select-prefix addition block for both modulo 2/sup n/-1 and diminished-one modulo 2/sup n/+1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.