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A Novel Distributed Amplifier With High Gain, Low Noise, and High Output Power in ${\hbox{0.18-}} \mu{\hbox {m}}$ CMOS Technology

65

Citations

15

References

2013

Year

Abstract

A new distributed amplifier (DA) topology is proposed, which is a combination of the conventional DA and the cascaded single-stage DA. This DA topology can provide wide bandwidth with considerations of the gain, noise figure (NF), and output power simultaneously, and requires reasonable dc power consumption. In this paper, two termination methods of this combination are investigated. From the measurements, the first DA proposed by Chen etal in 2011 has a small-signal gain of 20.5 dB, a 3-dB bandwidth of 35 GHz, and a gain-bandwidth (GBW) product of 371 GHz. The maximum output power at 1-dB output compression point (OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> ) is 8.6 dBm and the NF is between 6.8-8 dB at frequencies lower than 18 GHz. The chip size, including testing pads, is only 0.78 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the ratio of the GBW to chip size is 476 GHz/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The second DA has a small-signal gain of 24 dB, a 3-dB bandwidth of 33 GHz, and a GBW product of 523 GHz. The maximum OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> is 9 dBm and the NF is between 6.5-7.5 dB at frequencies lower than 18 GHz. The chip size including testing pads is only 0.83 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the ratio of the GBW to chip size is 630 GHz/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the authors' knowledge, the second circuit has the highest ratio of GBW to chip area and the highest figure-of-merit in 0.18- μm CMOS, and it has a comparable performance with other DAs in advanced process.

References

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