A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13- <inline-formula> <tex-math notation="LaTeX">$\mu\mbox{m}$</tex-math></inline-formula> CMOS Process

Abstract

This brief presents a fully integrated frequency synthesizer for software-defined radios covering not only all the existing wireless standards from 47 MHz to 10 GHz [including 14-band multiband orthogonal frequency-division modulation (MB-OFDM) ultrawideband (UWB)] but also the gigabits per second wireless communication around 60 GHz. A dual-band quadrature output voltage-controlled oscillatior reconfigurable as either a one-port oscillator for low power consumption or a two-port oscillator for low phase noise is employed as the core to generate all the frequencies from 47 MHz to 6 GHz. A multimode x3/x5/x7 injection-locked frequency multiplier and a single-sideband mixer with a tunable transformer-based narrow-band load are proposed to generate the carrier frequencies for the 14 MB-OFDM and impulse UWB bands with fast settling time, low power, and small chip area. An automatic amplitude calibration (APC) technique is proposed to greatly increase the locking range of the subharmonic injection-locked oscillators with achieving a given output amplitude. Implemented in a 0.13-μm CMOS process, the synthesizer prototype occupies an active area of 3 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , consumes 33-83 mW in total, and measures phase noise of -139.6 dBc/Hz at 3-MHz offset from a 1.7-GHz carrier.