An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18–20 dB of maximum gain and 3–3.5 dB of noise figure over 800 MHz to 6 GHz . A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around &lt;formula formulatype="inline"&gt;&lt;tex&gt;$+$&lt;/tex&gt;&lt;/formula&gt;70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards. </para>