Design and Verification of Serial Peripheral Interface

Abstract

The objective of this project is to design SPI Master Core using Verilog and verify the code using system verilog. Serial Peripheral Interface (SPI) is an interface that facilitates the transfer of synchronous serial data.SPI (Serial Peripheral Interface) is a synchronous serial data link that operates in full duplex mode. It communicates in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select line .Serial Peripheral Interface of symmetrical structure can be synthesized using Xilinx 12.3, and then can be simulated using Questa 10.0b. It is a popular interface used for connecting peripherals to each other and to microprocessors. The verification of the project is done using system verilog.