Study of Various Full Adders using Tanner EDA Tool

Abstract

Adders are key components in digital design, performing not only addition operations, but also many other functions such as subtraction, multiplication and division. Adders of various bitwidths are frequently required in Very Large-Scale Integrated circuits (VLSI) from processors to Application Specific Integrated Circuits (ASICs). Recently reported logic style comparisons based on full-adder circuits claimed Complementary Pass transistor Logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. Even Adder designed using Bi-CMOS technology can have more power as well as speed than that using CMOS technology. The most important and widely accepted matrics for measuring the quality of adder designs propagation delay, power dissipation and area. By improving the arithmetic circuits, the overall performance can be significantly improved. This paper describes the comparative performance of 1-bit full adder & three 4-bit adders designed using TANNER EDA, using different CMOS logic design styles. The CMOS Adder with best performance has also been realized using Bi-CMOS technology to get even better power-delay product.