A 10b 50MS/s pipelined ADC with opamp current reuse

Abstract

Power-saving techniques such as opamp current reuse and capacitive level shift reduce the power consumption of a 10b pipelined ADC to 220μW/MHz. A 50MS/S prototype in 0.18μm CMOS consumes 18mW (11mW for analog) at 1.8V and occupies 1.1times1.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured ENOB of the ADC is 9.2b (8.8b) for a 1MHz (20MHz) input