A 0.4 ps-RMS-Jitter 1–3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents the design and experimental results of a 0.4 ps rms jitter (integrated from 3 kHz to 300 MHz offset at 2.5 GHz) 1–3 GHz tunable ring-oscillator PLL for integrated clock multiplier applications. A new loop filter structure based on a sample-reset phase-to-voltage converter and a <emphasis emphasistype="boldital">Gm-C</emphasis> filter decouples reference spur performance from charge-pump current matching and loop filter leakage, while enables phase error preamplification to lower PLL in-band noise without reducing VCO analog tuning range or increasing loop filter capacitor size. The ring-oscillator VCO features programmability of phase noise and power consumption at a given frequency. The PLL is implemented in a digital 0.13 <formula formulatype="inline"><tex Notation="TeX">$\mu{\hbox{m}}$</tex></formula> CMOS process using only 1.2 V devices, occupies 0.07 <formula formulatype="inline"><tex Notation="TeX">${\hbox{mm}}^{2}$</tex> </formula> and consumes 23 mW excluding reference clock receiver for 2.5 GHz output at the lowest phase noise mode. </para>