A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link

Abstract

The first CMOS “gearbox LSI” based on 65-nm CMOS technology—namely, a 2-W 100-Gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer—was developed. Its power dissipation is 75% lower than that of a conventional SiGe-based gearbox LSI. To develop this low-power gearbox LSI, the power dissipation of its 25-Gb/s interface is decreased to 14 mW/Gb/s by three circuit schemes: maximizing the use of CMOS circuits, adopting a low-power circuit architecture for a current-mode-logic (CML) circuit, and minimizing clock distribution by using a flip-flop with a single-clock operation and a PLL with phase rotation for each channel. The 25-Gb/s interface in the LSI provides a transmitter output with sufficient eye opening and achieved minimum input sensitivity of 34.4-mV (peak-to-peak).