CMOS-SRAM soft-error simulation system

Abstract

We present a soft-error simulation system for designing CMOS-SRAM cells. We proposed a new noise current model and combined it with the SRAM's equivalent circuit. Using a three-dimensional topography simulator and considering the Rutherford scattering, we obtained the exact injection probability. The simulation results agree with those from a compulsory exposure experiment. Our system predicts the field soft-error rate from the alpha-particle emission rate, mask layout, and process conditions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>