An integrated reset/pulse pile-up rejection circuit for pixel readout ASICs

Abstract

We present a compact and low power integrated circuit designed to control the reset and perform pulse pile-up rejection in multi-channel spectroscopic-grade ASICs. The circuit has been implemented in a 0.35 mum CMOS technology using an area of 60times80 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and null static power consumption. These features make this circuit suitable to be embedded into the front-end readout cells for spectroscopy/imaging X- and gamma-ray pixel detectors