A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm

Abstract

The implementation of the SubBytes (or S-Box) step of the AES algorithm significantly contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-Box implementations, we use full-custom 256×8-bit ROMs, which significantly improve performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption accelerator using ROM-based S-Boxes in 65nm bulk CMOS which operates at 2.2GHz and consumes 523mW at 1.0V, 27°C. In counter-mode operation (CTR), the throughput is 275.2Gbps, which is 5.2x higher than the highest ever reported in the literature to our knowledge.