IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2011 · 60 citations · 20 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsComputer ArchitectureReconfigurable ComputingCoarse-grained Reconfigurable ArchitecturesGraphics Processing Unit ArchitectureGraphics Processing UnitsHardware AccelerationReconfigurable AcceleratorsReconfigurable System ArchitectureApplication-specific AccelerationFloating-point ArithmeticHardware MappingInteger Linear ProgrammingPerformance Optimization In Reconfigurable SystemsReconfigurable Architectures
Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their performance and flexibility. However, their applications have been restricted to domains based on integer arithmetic since typical CGRAs support only integer arithmetic or logical operations. This paper introduces approaches to mapping applications onto CGRAs supporting both integer and floating-point arithmetic. After presenting an optimal formulation using integer linear programming, we present a fast heuristic mapping algorithm. Our experiments on randomly generated examples generate optimal mapping results using our heuristic algorithm for 97% of the examples within a few seconds. We observe similar results for practical examples from multimedia and 3-D graphics benchmarks. The applications mapped on a CGRA show up to 120 times performance improvement compared to software implementations, demonstrating the potential for application acceleration on CGRAs supporting floating-point operations.
20
DRESC: a retargetable compiler for coarse-grained reconfigurable architectures
Bingfeng Mei, Serge Vernalde, Diederik Verkest et al. · 2003 · 207 citations
Edge-centric modulo scheduling for coarse-grained reconfigurable architectures
Hyunchul Park, Kevin Fan, Scott Mahlke et al. · 2008 · 197 citations
Space-time scheduling of instruction-level parallelism on a raw machine
Walter Lee, Rajeev Barua, Matthew I. Frank et al. · 1998 · 179 citations