IEEE Journal of Solid-State Circuits · 1972 · 22 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignMemory DevicesMemory Subsystem DesignBipolar Junction Transistor BiasingMemory Cell DesignMemory Circuit DesignMemory CircuitsNode VoltageNon-volatile Memory DesignParallel ProcessingSilicon
The authors describe the design of two high-density MOS associative memory cells. The first cell is suitable for data management applications, having three internal states including the DON'T CARE (mask) condition. The second cell is suitable for parallel processing applications and has the capability of selected bit writing. Both cells consume about 20 mil/SUP 2/ of silicon area, which allows the implementation of 512 bits on a chip. Varactor bootstrapping is used to enhance the storage node voltage for improved cell operation. The use of a compatible bipolar transistor is discussed.
1
J. Karp, W.M. Regitz · 1972 · 23 citations
Engineering, Computer Engineering, Electrical Engineering +15