Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures

TLDR

Three‑dimensional circuits that integrate logic, memory, optoelectronic, RF devices, and MEMS are being developed, but their higher heat load per surface area creates significant thermal‑management challenges. The study theoretically investigates cooling of 3D circuits using an integrated microchannel network. The authors model boiling convection in microchannels with one‑dimensional conservation equations and embed the results in a thermal resistance network to predict temperature distributions across logic and memory layers. The model shows that integrated microchannel cooling can dissipate up to 135 W cm⁻², keeping maximum temperatures at 85 °C, and allows more active layers while preserving external surface area for signal transmission.

Abstract

The semiconductor community is developing three-dimensional circuits that integrate logic, memory, optoelectronic and radio-frequency devices, and microelectromechanical systems. These three-dimensional (3D) circuits pose important challenges for thermal management due to the increasing heat load per unit surface area. This paper theoretically studies 3D circuit cooling by means of an integrated microchannel network. Predictions are based on thermal models solving one-dimensional conservation equations for boiling convection along microchannels, and are consistent with past data obtained from straight channels. The model is combined within a thermal resistance network to predict temperature distributions in logic and memory. The calculations indicate that a layer of integrated microchannel cooling can remove heat densities up to 135W/cm2 within a 3D architecture with a maximum circuit temperature of 85°C. The cooling strategy described in this paper will enable 3D circuits to include greater numbers of active levels while exposing external surface area for functional signal transmission.