Protocol control VLSI for broadband packet communications

Abstract

Processing algorithms and architecture for a protocol control VLSI are presented. Parallel processing algorithms, buffer management functions, and direct execution of high-level protocol description language are introduced. The VLSI provides high-speed, high-throughput protocol processing for broadband packet communications systems. It uses CMOS technology and can handle X.25-based packet protocols (layers 2 and 3) at data rates of up to 50 Mb/s. The performance of a high-speed packet switching system incorporating this VLSI is evaluated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>