All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture

TLDR

The split‑ADC architecture allows fully digital calibration of capacitor‑mismatch nonlinearity in a SAR ADC. The die is divided into two independent halves that each convert the same input, and their outputs are averaged while their difference drives a background calibration algorithm that uses LMS feedback to estimate and correct capacitor‑mismatch errors, aided by a novel segmentation and shuffling scheme that supports a wide input range. Simulations of a 16‑bit 1 Msps SAR ADC in 180 nm CMOS demonstrate calibration convergence within 200 000 samples.

Abstract

The “split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a successive approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal. Total area and power is unchanged, resulting in minimal increase in analog complexity. For each conversion, the half-sized ADCs generate two independent outputs which are digitally corrected using estimates of capacitor mismatch errors for each ADC. The ADC outputs are averaged to produce the ADC output code. The difference of the two outputs is used in a background calibration algorithm which estimates the error in the correction parameters. Any nonzero difference drives an LMS feedback loop toward zero difference which can only occur when the average error in each correction parameter is zero. A novel segmentation and shuffling scheme in the SAR capacitive DAC enables background calibration for a wide range of input signals including dc. Simulation of a 16 bit 1 Msps SAR ADC in 180 nm CMOS shows calibration convergence within 200 000 samples.