IEEE Transactions on Microwave Theory and Techniques · 2006 · 16 citations · 20 references
EngineeringElectrical EngineeringMicroelectronicsMicrowave EngineeringSemiconductor DevicesActive FiltersCmos Circuit DesignIntegrated Circuit DesignMicrowave FiltersMicrowave Integrated CircuitsRadio-frequency Integrated CircuitsBandpass FilteringBandpass FiltersBandwidthFiltersIntegrated FiltersNoise FigureRecursive FilterTuning Range
In this paper, two silicon-integrated differential active bandpass filters are presented. The first one is a recursive filter based on a cellular approach. This circuit is independently tunable in terms of power transmission gain, center frequency, and bandwidth. The chip surface is less than 1.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . For this prototype, measurements demonstrate a 1.9-2.4-GHz center-frequency tuning range with a typical gain of 15 dB and a 3-dB bandwidth of 60 MHz. Gains of up to 40 dB and bandwidths as low as 20 MHz are also achievable in the 2.05-2.38-GHz range. Subsequently, the design of an integrated three-branch channelized bandpass filter is addressed. The proposed filter uses an active power splitter at its input. Moreover, the channels are based on elementary first-order tunable recursive stages derived from the previously described topology, thus making the overall filter fully reconfigurable. This second circuit, whose layout size is smaller than 3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , can exhibit 3-dB bandwidths of ap90 MHz and gains of up to 20 dB within a 1.95-2.23-GHz tuning range. Controllable high selectivity for each rejected band can be obtained through the generation of adjustable out-of-band transmission zeros. Furthermore, a dual-band behavior is also feasible through this filter. To conclude, an original method to extract the exact noise figure of differential circuits is reported, and applied to the filter prototypes developed in this study. The Philips QUBIC4 0.25-mum silicon BiCMOS process has been used for the design of the two circuits presented
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