The Superjunction Insulated Gate Bipolar Transistor Optimization and Modeling

Abstract

In this paper, we present a detailed analysis and optimization of the superjunction (SJ) insulated gate bipolar transistor (IGBT). The SJ IGBT is a new device that breaks the IGBT limits, i.e., it delivers performance that is dramatically better. More specifically, we demonstrate here that the optimized SJ IGBT can deliver turn-off losses that are at least 50% lower than those of the state-of-art IGBT while maintaining a similarly low on-state performance, both at room temperature and at higher temperatures. The presence of alternating p- and n-pillars in the drift region gives rise to unique characteristics that when optimized can deliver superior performance. This paper also presents a SPICE model of the SJ IGBT under optimized conditions. Its results are in good agreement with the DESSIS simulation results under direct current conditions. This model consists of an intrinsic MOSFET and a parallel combination of wide- and narrow-base p-n-p bipolar junction transistors.