High current regimes in transistor collector regions

Abstract

The falloff of transistor gain and cutoff frequency at high currents is a familiar phenomenon. We show here, for the case of transistors having epitaxial collectors, how the mechanism responsible for the falloff depends upon device operating conditions. At any V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cb</inf> , a current can be calculated above which falloff begins. If the magnitude of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cb</inf> is lower than a critical value V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</inf> , falloff will occur because the transistor enters a saturation or quasi-saturation mode of operation. If the magnitude of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cb</inf> is greater than V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</inf> , falloff will occur because the transistor enters a mode of operation associated with space-charge-limited flow. We illustrate the usefulness of this description in understanding observed device behavior, and show how it enables a new interpretation to be given to experimental results previously reported. Important implications for transistor modeling are also discussed.