A 12-bit, 200-MS/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end

Abstract

A high-speed, low-power pipeline ADC is realized by replacing the front-end residue amplifiers with pulsed bucket brigade circuitry and compensating for the introduced errors using digital linearization. The ADC is implemented in 65-nm CMOS and occupies 0.26 mm2. It operates at 200 MS/s, consumes 11.5 mW from a 1-V supply and achieves an SNDR of 65 dB at low input frequencies and 57.6 dB near Nyquist. The corresponding SNDR-based Schreier FOM is 164.5 dB and 157 dB, respectively.