RF ESD protection strategies - the design and performance trade-off challenges

Abstract

ESD protection strategies utilized in RF circuit applications in CMOS and BiCMOS technologies are investigated and the results are presented in this paper. The conventional approach using diodes with power clamp is compared with novel approaches such as plug-and-play passive elements and full or partial circuit-ESD co-design. The trade-offs are discussed from both RF and ESD point of views. Common problems as parasitic ESD current discharge paths and voltage overshoot are discussed and solutions are proposed