Silicon-on-Sapphire Complementary MOS Memory Cells

Abstract

Complementary MOS circuitry offers the advantages of high-speed, low-quiescent power dissipation, and loose device parameter tolerances. However, only with the recent development of clean technology has it been possible to fabricate stable devices. The advances in silicon-on-sapphire epitaxy have permitted the development of a high-speed low-power complementary MOS circuit module. This paper describes the circuit, its operation, the method used in fabricating it in silicon-on-sapphire, and the switching performance of the circuit. The basic memory cell is a NDRO flip-flop with feedback supplied through a transmission gate. The total circuit delay from write command to output sense signal is 5 to 7 ns at a standby power dissipation of 7 to 20 /spl mu/ W. To show the feasibility of adapting silicon-on-sapphire complementary MOS technology to LSI, a 9-bit word (1-byte) was constructed. The entire module containing 54 N-channel and 36 P-channel devices dissipated less than 100 /spl mu/ W in a standby condition.