A 25Gb/s CDR in 90nm CMOS for High-Density Interconnects

Abstract

A CDR for source-synchronous high-density link applications receives 25Gb/s at a BER of <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The CDR is a first-order bang-bang topology employing a phase interpolator, linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter. The core CDR circuit occupies 0.09mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 98mW from a 1.1V supply