The effect of copper contamination on field overlap edges and perimeter junction leakage current

Abstract

This work demonstrates that copper contamination present on pre gate-oxidation silicon surfaces results in yield and reliability problems particularly at field overlap edges. Similarly, the junction leakage current associated with the junction perimeter dominates the total leakage current. These detrimental device effects are shown to be caused by copper that is present close to the silicon surface even after thermal processing. Because field overlap and junction perimeter defects become relatively more important when the critical dimensions of circuits are scaled to smaller sizes, they dominate yield loss of high-density circuits, magnifying their importance for future technology generations.