Predictive yield modeling for reconfigurable memory circuits

Abstract

This paper presents a novel approach to the modeling of defect related yield losses in reconfigurable memory circuits. The proposed approach is based on the critical area extracted from the memory layout and the in-line defect inspection data. A complete chip level yield model that takes into account the actual redundancy scheme is presented, with the demonstration of excellent accuracy between the model prediction and bitmap data from an actual flash memory product manufactured by Intel Corporation.